Zarlink Demonstrates World's Highest-Density Single-Chip Packet Processor for Metro Ethernet at SUPERCOMM2003

Using its newest packet processor technology, Zarlink will demonstrate seamless interworking between TDM circuit-switched facilities and packet networks by transporting T1/E1 TDM voice with carrier-class quality over a next-generation, metropolitan Ethernet network. Hosted by the MEF (Metro Ethernet Forum), the demonstration network will showcase the interoperability of Ethernet equipment and components from 28 MEF member companies, including Zarlink, and illustrate a variety of newly defined services for optical Ethernet networks.

The TDM-to-Ethernet interworking achieved by Zarlink's packet processor - a capability known as CESoP (circuit emulation services over packet) - is described by Zarlink's lead customers as an important "enabling technology" for the adoption of optical Ethernet technology in metro networks.

More than 85% of the traffic carried over today's metro and wide-area optical networks is data. MEF member companies and other industry leaders want to support this traffic more efficiently by offering new classes of Ethernet- based data services. To a large extent, the success of these new services hinges on their ability to interoperate with the huge installed base of TDM access networks, and the profitable TDM services they carry.

"Our packet processor will help accelerate the migration to metro Ethernet networks by allowing Ethernet equipment to transport high volumes of TDM services with carrier-grade quality," said Jeremy Lewis, product line marketing manager, Packet Processors, Zarlink Semiconductor. "Participating in the MEF interoperability demo is public proof that we deliver true, standards- based TDM-to-Ethernet interworking."

Comprehensive CESoP demonstration

At the MEF SUPERDemo, two Zarlink CESoP evaluation boards, each with a packet processor, will demonstrate error-free operation of a T-line (TDM line) across the MEF's new E-line (Ethernet point-to-point) service. The TDM interfaces on Zarlink's boards will be connected to handsets via PCM CODECs (pulse code modulation coder/decoder), or to E1 testers via LIUs (line interface unit). The boards' Ethernet ports will be connected to the metro Ethernet network via off-the-shelf PHYs (physical layer device).

As part of the SUPERDemo at Booth 10115, Zarlink will demonstrate the capability of its new chip to provide synchronization across an Ethernet network. One evaluation board will be set to operate as clock master and the other as slave. The synchronization lock between them will be shown on a digital oscilloscope.

High-density, carrier-grade packet processor

Zarlink's newest packet processor is an efficient, high-density, single- chip CESoP engine. The chip simultaneously delivers CES for 32 T1/E1 lines, or 1,024 TDM circuits.

Zarlink's chip combines this high-density capability with carrier-grade TDM QoS (quality of service). A key QoS challenge with CESoP is achieving the precise levels of network synchronization and clocking required to reliably deliver constant bit-rate voice traffic over variable bit-rate packet networks. Zarlink's device overcomes this challenge, in part, with patent- pending software technology for both adaptive and differential synchronization.

Zarlink's new packet processor is also extremely flexible, allowing each T1/E1 channel to run on its own synchronization clock. The chip complies fully with synchronization requirements in the ITU-T's (International Telecommunication Union-Telecommunications) G.823 and G.824 recommendations for T1/E1 links, and ANSI's (American National Standards Institute) T1.101 standard.

Sampling now with lead customers

Global equipment vendors are evaluating samples of Zarlink's new CESoP packet processor for use in metro Ethernet equipment. The device, which Zarlink anticipates releasing for sale later this year, complements the MT90880/1/2/3 family of packet processors introduced in October 2002.

For information about the new packet processor, please contact Jeremy Lewis at jeremy.lewis@zarlink.com. For information on Zarlink's MT90880/1/2/3 chips, visit http://products.zarlink.com/profiles/MT90880. For information on the MEF, visit www.metroethernetforum.org/.

About Zarlink Semiconductor

For almost 30 years, Zarlink Semiconductor has delivered semiconductor solutions that drive the capabilities of voice, enterprise, broadband and wireless communications. The company's success is built on its technology strengths, including voice and data networks, consumer and ultra low-power communications, and high-performance analog. For more information, visit http://www.zarlink.com/.

Certain statements in this press release constitute forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. Such forward-looking statements involve known and unknown risks, uncertainties, and other factors which may cause the actual results, performance or achievements of the Company to be materially different from any future results, performance, or achievements expressed or implied by such forward-looking statements. Such risks, uncertainties and assumptions include, among others, the risks discussed in documents filed by the Company with the Securities and Exchange Commission. Investors are encouraged to consider the risks detailed in those filings.

Zarlink, ZL, and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

CONTACT: Zarlink, Michael Salter, Media Relations,
613 270-7115, michael.salter@zarlink.com; United States, Natalie Sauve,
High Road Communications, 613 236-0909, nsauve@highroad.com; Europe, June
Stokes, Pinnacle Marketing Communications, 44 208-869-9345,
june@pinnacle-marketing.com